Semiconductor memory testing device

ABSTRACT

This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular block after a failure is detected in the block. In the test system which tests writing and erasing as a unit of block in the memory under test by using a match function includes a register ( 61 ) provided for each memory under test (MUT n ) for holding a first failure generated in a particular block at a first control signal (Ca) from a pattern generator ( 2 ), establishes a match condition, a pass condition, and a write inhibit condition for the particular block for test cycles after the first failure; and resets the register at a cycle specified by a second control signal (Cb) from the pattern generator to release the match condition, pass condition, and write inhibit condition.

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor memory testsystem which is capable of reducing a test time for testingsemiconductor memory devices such as flash memories.

BACKGROUND OF THE INVENTION

[0002] An example of the conventional technology regarding suchsemiconductor memory test system will be explained with reference toFIGS. 3-5.

[0003] As shown in FIG. 3, the main components of the conventionalsemiconductor memory test system include a timing generator 10, apattern generator 20, a wave formatter 30, and a logic comparator 40.

[0004] Peripheral devices and a tester processor are, however,abbreviated in the drawing for simplicity.

[0005] Under this arrangement, the tests for MUT₁-MUT_(n), which arememory devices under test, are conducted by executing the test program.

[0006] Normally, the semiconductor memory test system tests severalmemory devices simultaneously in order to improve production efficiency.

[0007] The timing generator 10 generates a reference clock and a strobetiming signal.

[0008] Pursuant to the test program produced in advance, the patterngenerator 20 outputs an address signal ADRS, a write data signal WD, acontrol signal CS, and expected value data ED, which are synchronizedwith the reference clock from the timing generator 10.

[0009] The wave formatter 30 receives the address signal ADRS, the writedata signal WD, and the control signal CS from the pattern generator 20to format the waveforms into test signals, and supplies the test signalsto the memories under test MUT₁-MUT_(n).

[0010] The write and read operation of the test data for the memorydevices under test MUT₁-MUT_(n) is controlled by the control signal CS.

[0011] The logic comparator 40 detects whether there is a match betweenthe data read from the memory devices under test MUT₁-MUT_(n) at thetiming of the strobe signal STRB from timing generator 10 and theexpected value data. The logic comparator 40 determines the pass/fail ofthe memories devices under test MUT₁-MUT_(n) based on the result of thecomparison at the cycle of CPE=“1”.

[0012] Next, the operation of the logic comparator 40 will be explainedwith reference to FIG. 4 which shows the basic circuit structure of thelogic comparator.

[0013] Normally, the logic comparator 40 includes logic comparisoncircuits 4 ₁-4 _(n) which correspond to the memory devices under testMUT₁-MUT_(n).

[0014] Although each of the logic comparison circuits 4 ₁-4 _(n) in FIG.4 includes a comparison circuit corresponding to each data bit of theMUT, the data bits here is expressed as one bit in order to simplify thediagram.

[0015] In the logic comparison circuit 4 _(n), the test data signalRD_(n) that has been read out from DUT_(n) is latched by the timing ofthe strobe signal STRB from the timing generator. An EXNOR (exclusiveNOR) gate 70 detects whether there is a match between the latched dataand the expected value data EXP from the pattern generator. When thereis a match, the EXNOR gate 70 generates a match detection signal “1”.

[0016] The logic comparison (for determining pass or fail) is conductedby the CPE signal and the match detection signal noted above.

[0017] When a mismatch is detected in the cycle of CPE=“1”, the logiccomparison circuit determines a failure and outputs a fail detectionsignal FAIL=“1”.

[0018] When all the data read out from the memory devices under testMUT₁-MUT_(n) match the expected value data, a match flag signal MF isprovided to the pattern generator 20.

[0019] Next, the process of testing a flash memory will be explained inthe following.

[0020] When testing a flash memory, because of its operationalprinciple, data cannot always be set in the target memory cell by onewriting or erasing action. Rather, ordinarily, a flash memory requireswriting actions or erasing actions of several times.

[0021] Then, in the memory cell where the writing or erasing operationhas been correctly conducted, the memory is so designed that excesswriting and erasing actions, which are additional writing and erasingmotions with respect to the successful memory cell, are no longerallowed.

[0022] Further, the required number required for writing or erasingactions varies depending on, such as, the addresses of the flash memory.

[0023] One of the types of flash memories having the abovecharacteristic is called a NAND type flash memory. In the NAND flashmemory, the internal cells are structured as a unit of page where thewriting action is conducted as a unit of page.

[0024] For example, as shown in FIG. 5, in the memory having memorycells of 1,024 row by 4,224 column, each row is considered as one page.Thus, the memory is structure by 1,024 pages from 0 to 1,023 page.

[0025] Further, the erasing action in the NAND type flash memory isconducted by a unit of block which is a group of consecutive pages.

[0026] For example, in the example shown in FIG. 5, four (4) pages ofmemory cell constitute one block, thus, the flash memory is structuredby 0-255 blocks.

[0027] In testing a NAND type flash memory having the abovecharacteristic, a match function is used.

[0028] In the match function, sequence control of the test patterngeneration is conducted based on the result of the match signalexplained above.

[0029] When one memory MUT out of plural memories under testMUT₁-MUT_(n) shows a mismatch, writing and erasing test is conductedonce again with that address of the MUT.

[0030] At this time, in order to avoid the excess writing and erasingactions towards the MUT's addresses showing the match, a write enablesignal to the MUTs is prohibited.

[0031] When all the memory devices under test MUT₁-MUT_(n) are matchedwith the expected data, the operation then moves on to the nextaddresses and begins conducting another writing and erasing test.

[0032] When mismatch is repeated in the same memory cell for more than apredetermined number of times, the memory under test MUT is determineddefective.

[0033] When the data writing and erasing tests are correctly conductedfor all of memory cells of the addresses within the specified number oftimes, the MUTs will be considered non-defective.

[0034] In the NAND type flash memory, when the number of defectiveblocks is smaller than a predetermined number, the flash memory isconsidered non-defective, even though a defective block exists therein.

[0035] This is because a user of the memory recognizes that there aredefective blocks in the NAND type flash memory in advance so that he canarrange his design so that the defective blocks will not be used.

[0036] Incidentally, when determining the quality of the NAND type flashmemory, once a mismatch is detected for a target block of the memory,this block is determined as defective. Thus, there is no need to furthercontinue a logic comparison procedure for the block thereafter.

[0037] However, the conventional semiconductor memory test system doesnot includes such a function, therefore, it will continue the logiccomparison using the match function even after the defective block isrecognized.

[0038] Since the conventional semiconductor memory test system continuesthe logic comparison with use of the match function even after detectingthe defective block in the flash memory, a problem arises thatunnecessary test times have to be spent in the test.

DISCLOSURE OF THE INVENTION

[0039] Therefore, in order to solve the above noted problem, it is anobject of the present invention to provide a semiconductor memory testsystem in which, during the test for each unit of block in a flashmemory, the test system will not further conduct logic comparison for atarget block after a failure is detected in the block.

[0040] Namely, the present invention for achieving the above object is asemiconductor memory test system characterized in that the test systemcomprising a register provided for each memory device under test forholding a first failure generated in a particular block of a memoryunder test at a first control signal from a pattern generator;establishing a match condition, a pass condition, and a write inhibitcondition for the particular block for test cycles after the firstfailure; and resetting the register at a cycle specified by a secondcontrol signal from the pattern generator to release the matchcondition, pass condition, and write inhibit condition.

[0041] Further, the present invention is a semiconductor memory testsystem for testing a plurality of memory devices under test (MUT) byusing a match function where sequence control of test patterns areconducted based on the matched results between an output signal of eachMUT and an expected value signal from the pattern generator. Thesemiconductor memory test system is characterized in comprising aregister provided for each memory device under test for holding a firstfailure generated in a particular block at a first control signal from apattern generator; establishing a match condition, a pass condition, anda write inhibit condition for the particular block for a test cycleafter the first failure; and resetting the register at a cycle specifiedby a second control signal from the pattern generator to release thematch condition, pass condition, and write inhibit condition.

[0042] Further, in the semiconductor test system of the presentinvention, the above mentioned first control signal and second controlsignal are produced by the pattern generator based on the test patternprogram produced in advance.

[0043] Further, in the semiconductor memory test system of the presentinvention, the memory device under test is a flash memory where the datawriting action and data erasing action of several times for the sheaddresses is tested as a unit of block.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044]FIG. 1 is a block diagram of the semiconductor memory test systemof the present invention.

[0045]FIG. 2 is a circuit diagram of the logic comparison circuit in thesemiconductor memory test system of the present invention.

[0046]FIG. 3 is a block diagram of the conventional semiconductor memorytest system.

[0047]FIG. 4 is a circuit diagram of the logic comparison circuit in theconventional semiconductor memory test system.

[0048]FIG. 5 is a block diagram showing a structure in a flash memory.

BEST MODE IMPLEMENTING THE INVENTION

[0049] The present invention will be explained with reference to theembodiments in the following.

[0050] The embodiment of the present invention will be explained withreference to FIGS. 1 and 2.

[0051] As shown in FIG. 1, the semiconductor memory test system of thepresent invention is comprised of a timing generator 10, a patterngenerator 20, a wave formatter 30, a logic comparator 50, and AND gates8 ₁-8 _(n).

[0052] However, peripheral devices and a tester processor, as in theexplanation of the conventional technology, will be abbreviated in orderto make the diagrams simple.

[0053] In addition, since the timing generator 10, the pattern generator20, and the wave formatter 30 are the same as those in the conventionaltechnology, the explanation of these units will be omitted as well.

[0054] The logic comparator 50 conducts a match function by detectingwhether there is a match between the data from the memory devices undertest MUT₁-MUT_(n) and the expected value data at the timing of thestrobe signals STRB from the timing generator 10, and determinespass/fail of the memory devices under test MUT₁-MUT_(n) based on thematch results at a cycle of CPE=“1”.

[0055] Next, the operation of the logic comparator 50 will be explainedwith reference to FIG. 2.

[0056] Normally, the logic comparator 50 is formed with logic comparisoncircuits 5 ₁-5 _(n), which correspond to the memory devices under testMUT₁-MUT_(n). In FIG. 2, however, since each of the logic comparisoncircuits has the same structure, FIG. 2 shows only the logic comparisoncircuit 5 _(n).

[0057] Further, the logic comparison circuit 5 _(n) handles the sameamount of data bits as in the MUT, however, the data bit will bedisplayed as one bit in order to make the diagrams simple.

[0058] In the logic comparison circuit 5 _(n), the test data signalRD_(n) which is read out from memory under test MUT_(n) is latched in aregister 60 by the timing of the strobe signal STRB from the timinggenerator. The latched data is compared with the expected value data EXPfrom the pattern generator by the EXNOR gate 70 at the strobe signalSTRB, where a match detection signal “1” is output upon finding a matchtherebetween.

[0059] The logic comparison (for determining pass or fail) is conductedby a CPE signal and the match detection signal mentioned above.

[0060] When a mismatch is detected in the cycle of CPE=“1”, it the logiccomparison circuit determines a failure and outputs a failure detectionsignal FAIL=“1”.

[0061] Further, the failure detection signal FAIL is provided to a holdregister 61 through an OR gate 75, where the failure detection signal isloaded therein by a control signal Ca.

[0062] Once the failure signal is loaded by the control signal Ca, theoutput of the hold register 61 is returned to the input of the OR gate75. Therefore, an attempt to load the pass condition in the cyclesthereafter is invalidated, thereby maintaining the failure condition inthe hold register 61.

[0063] Thus, once the failure is loaded by the control signal Ca, theoutput from the hold register 61 is provided to an AND gate 74 throughan inverter 72 to act as a logic comparison inhibit signal of logic “1”thereby prohibiting the CPE signal to the AND gate 73. Accordingly, theAND gate 73 which logically compares the match output of EXNOR gate 70is set to a pass condition.

[0064] Further, since the output of the hold register 61 is connected toan input of an OR gate 76, a match signal of MUT_(n) is maintained as“1”.

[0065] Therefore, when the failure is generated in a particular block ofthe memory under test, the match condition will be maintained thereafterwith respect to that memory block.

[0066] Further, the output of the hold register 61 also acts as a writeenable inhibit signal, and as shown in FIG. 1, is provided to an ANDgate 8 _(n), thereby prohibiting the writing operation of the MUT_(n).

[0067] Here, the control signals Ca and Cb transmitted from the patterngenerator 20 can be generated at arbitrary cycles by programming, inadvance, their timings in the test pattern.

[0068] The flash memory testing by the semiconductor test system of thepresent invention is explained in the following.

[0069] In the flash memory testing, in the logic comparison cycle withinthe writing and erasing test for each test block, the control signal Cais generated and when a failure is generated in a memory cell within aparticular block, the match condition for the memory device under testis mandatorily maintained so as to produce a pass result in the logiccomparison and the writing operation thereafter is prohibited.

[0070] In addition, before proceeding to the next block, the controlsignal Cb is generated at the end of each block to reset the holdregister 61 to be prepared for the test on the next block.

Industrial Applicability

[0071] The present invention is implemented in the manner explained inthe foregoing, thereby achieving the following effects.

[0072] Namely, in the semiconductor memory test system of the presentinvention, when a failure is detected with respect to a particularmemory block, a match condition is maintained for that block to prohibitany further writing or erasing operations for the block, resulting inthe reduction of the test time.

What is claimed is:
 1. A semiconductor memory test system characterizedin that: the test system comprising a register provided for each memorydevice under test for holding a first failure generated in a particularblock at a first control signal from a pattern generator; establishing amatch condition, a pass condition, and a write inhibit condition for theparticular block a test cycle after the first failure; and resetting theregister at a cycle specified by a second control signal from thepattern generator to release the match condition, pass condition, andwrite inhibit condition.
 2. A semiconductor memory test system fortesting a plurality of memory devices under test (MUT) by using a matchfunction where sequence control of test patterns is made based onresults of match between an output signal of each memory device undertest (MUT₁, MUT₂, . . . , MUT_(n)) and an expected value signal from apattern generator (20) characterized in that: the test system comprisinga register (61) provided for each memory device under test for holding afirst failure generated in a particular block at a first control signal(Ca) from a pattern generator; establishing a match condition, a passcondition, and a write inhibit condition for the particular block fortest cycles after the first failure; and resetting the register at acycle specified by a second control signal (Cb) from the patterngenerator to release the match condition, pass condition, and writeinhibit condition.
 3. The semiconductor test system as defined in claim2, wherein the first control signal (Ca) and the second control signal(Cb) are produced by the pattern generator (20) based on test patternsprogrammed in advance.
 4. The semiconductor test system as defined inclaim 2, wherein Further, each memory device under test (MUT₁, MUT₂, . .. , MUT_(n)) is a flash memory where data writing and erasing actions ofseveral times for the same addresses are tested as a unit of block.